A Schottky barrier device is a type of semiconductor device that utilizes the properties of a potential barrier formed between a metal-semiconductor junction to perform one or more functions. A typical Schottky barrier device may include a wide band-gap semiconductor layer, on which one or more metal contacts are placed to form a Schottky interface. Some exemplary Schottky barrier devices include Schottky diodes, high electron mobility transistors (HEMTs), and metal-semiconductor field-effect transistors (MESFETs). A HEMT incorporates a junction between one or more HEMT epilayers having a first band-gap and a semiconductor layer having a second band-gap (i.e., a heterojunction), at which a two-dimensional electron gas is formed, allowing electrons to flow between a drain contact and a source contact. The potential barrier formed by a Schottky interface between a gate contact metal and the semiconductor layer is used to control the flow of electrons through the channel. Similarly, a MESFET uses a doped channel located in a semiconductor layer to allow electrons to flow between a drain contact and a source contact. Again, the potential barrier formed by a Schottky interface between a gate contact metal and the semiconductor layer is used to control the flow of electrons through the doped channel.
The geometry of the contact metal that forms the Schottky interface with the semiconductor layer may dictate several performance characteristics of the Schottky barrier device. For example, the speed of the Schottky barrier device may be directly related to the geometry of the contact metal. Generally, the smaller the area of the contact metal at the surface of the semiconductor layer where the Schottky interface is formed, the faster the Schottky barrier device can operate. Accordingly, many methods for forming contacts for a Schottky barrier device have focused on reducing the area of the contact metal at the surface of the semiconductor layer.
FIGS. 1A-1C and the accompanying flow chart shown in FIG. 2 show a conventional process for creating a Schottky contact in a Schottky barrier device. To begin, a first dielectric layer 10 is provided on a first surface of a semiconductor layer 12 (FIG. 1A and step 100). The first dielectric layer 10 is then etched to form a contact window 14, through which a portion of the first surface of the semiconductor layer 12 is exposed (FIG. 1B and step 102). Notably, the etching process is a conventional photo-resist etching process, in which a photo-resistive mask is applied on top of the first dielectric layer 10 and patterned, and the portions of the first dielectric layer 10 exposed through the photo-resistive mask are etched away. As will be appreciated by those of ordinary skill in the art, conventional photo-resist etching processes lack the precision required to create features below a certain size. Accordingly, the lower limit of the area of the contact window 14 is constrained by the photo-resist etching process. Finally, a contact metal 16 is deposited on the portion of the first surface of the semiconductor layer 12 exposed through the contact window 14 (FIG. 1C and step 104). As shown in FIG. 1C, a length 18 of the contact metal 16 at the first surface of the semiconductor layer 12 corresponds with the dimensions of the contact window 14, and is therefore constrained by the precision of the photo-resist etching process.
FIGS. 3A-3E and the accompanying flow chart shown in FIG. 4 show a process for creating a Schottky contact for a Schottky barrier device with improved precision, as described in U.S. Pat. No. 8,357,571, which is incorporate herein by reference in its entirety. To begin, a first dielectric layer 20 is provided on a first surface of a semiconductor layer 22 (FIG. 3A and step 200). The first dielectric layer 20 is then etched to form a first opening 24, through which a portion of the first surface of the semiconductor layer 22 is exposed (FIG. 3B and step 202). Notably, the etching process is a conventional photo-resist etching process, as described above. Accordingly, the lower limit of the area of the first opening 24 is constrained by the photo-resist etching process used to generate the opening. In an attempt to control the area of the first opening 24 with additional precision, a second dielectric layer 26 is provided on a surface of the first dielectric layer 20 opposite the semiconductor layer 22 and in the first opening 24 (FIG. 3C and step 204). A first portion of the second dielectric layer 26 is then etched away, leaving a second portion of the second dielectric layer 26 on the sidewalls of the first opening 24 (FIG. 3D and step 206). The second portion of the second dielectric layer 26 defines a contact window 28, which is smaller than the area of the first opening 24, and through which a portion of the first surface of the semiconductor layer 22 is exposed. A contact metal 30 is then deposited on the portion of the first surface of the semiconductor layer 22 exposed through the first opening 24, as modified by the second dielectric layer 26 (FIG. 3E and step 208). Using the second dielectric layer 26 to modify the first opening 24 allows the area of the contact window 28 to be controlled to a greater degree of precision, thereby decreasing a length 32 of the contact metal. However, the process described above may still have difficulty creating contacts below a certain size. Accordingly, there is a need for a process for precisely manufacturing contacts for semiconductor devices with precise geometries.